Semiconductor device manufacturing methods often employ back end of line (BEOL) processes to add interconnect wiring to integrated circuit (IC) devices. For example, in numerous applications, multiple layers of dielectric material (often referred to as interlayer dielectric, or ILD) are formed on a chip. The layers of dielectric material are patterned and etched to form trenches that are later filled with conducting material (e.g., copper) to form vias and wires that connect devices (e.g., RAM) in the chip to other components (e.g., motherboard). Conventional high speed chips may have as many as five to ten wiring layers.
Historically, dense metal oxides such as, for example, silicon dioxide (SiO2), have been used as the dielectric material in interconnect structures. While SiO2 is an excellent insulator with high modulus and hardness, and has a coefficient of thermal expansion (CTE) close to silicon, the dielectric constant (k) is approximately 4.0, which is too high for advanced generation interconnects. High-dielectric constants for ILD materials result in signal charging and propagation delays as well as increased transistor power budgets in the circuits that make up the IC. These circuit delays and power requirements are becoming an issue relative to improving the performance of IC chips. As such, device manufacturers are migrating toward the use of low-k (e.g., k<3.0) dielectric materials (such as, for example, inorganic polymers, organic polymers such as polyamides, spin-on glasses, silsesquioxane-based materials, etc.). Generally speaking, low-k dielectric materials serve to increase the speed of the conducting wires, thereby increasing the speed of the semiconductor device.
However, one concern of integrating low-k dielectric materials into the wafer BEOL is the delamination stresses that occur when the chip is packaged. The delamination of the chip in the low-k dielectric material layers due to their weaker mechanical properties (e.g., modulus and adhesion) may result in failure of the package.
Stresses are imparted to the chip due to differences in CTE between the chip and the different materials used in semiconductor packaging. For example, a Silicon chip has a relatively low CTE, while an organic carrier that the low-k chip is disposed upon may have a relatively high CTE. Also, each wiring level may be composed of a different low-k dielectric material, each having differing coefficients of thermal expansion. When the chip is assembled to an organic carrier at an elevated temperature and subsequently cooled, and when a chip undergoes thermal cycling during reliability testing, the differences in CTE between adjacent layers cause stresses at the interface between the layers.
These stresses can lead to structural damage of the chip, including cracks in individual layers and delamination between adjacent layers. Structural damage, in turn, renders a chip unusable, thereby decreasing yield and posing a reliability risk.
In the early stages of technology development, low-k dielectric material delamination is a problem that typically affects a large number of modules. In order to determine the failing interfaces, destructive failure analysis is often performed. However, destructive failure analysis has become a very fine art and is difficult, slow, and costly.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.